The present invention relates to a semiconductor device, and particularly to a technology which is effective when applied to a semiconductor device having MOSFETs and an SRAM which are disposed in a SOI substrate.
An SRAM (Static Random Access Memory) is a type of a semiconductor memory which stores data using a flip-flop. For example, in the SRAM, data (“1” or “0”) is stored in two cross-coupled CMOS inverters including four transistors. Since two transistors are required for a read access and a write access, in a typical SRAM, a memory cell includes six transistors. The CMOS is the abbreviation of Complementary MOS (Metal Oxide Semiconductor).
For example, Patent Document 1 (Japanese Unexamined Patent Publication No. 2004-200702) shown below discloses a semiconductor memory device including eight transistors N1 to N6 and P1 and P2, in which the two PMOS transistors P1 and P2 and the six NMOS transistors N1 to N6 are respectively arranged in one N-well and one P-well each formed in a semiconductor substrate, and the N-well is disposed in one corner of a memory cell (see the paragraphs [0037] to [0048] and FIGS. 3 to 5).
Also, Patent Document 2 (Japanese Unexamined Patent Publication No. 2002-353340) shown below discloses a semiconductor storage device including a data storage portion 20 in which data is stored, and a transfer gate portion having a MOSFET 12 of a first conductivity type for writing data into the data storage portion and reading data from the data storage portion. As a substrate bias for the MOSFET 12, a potential corresponding to the data stored in the data storage portion is applied thereto (see the paragraphs [0020] to [0025] and FIGS. 2 and 3).
Also, Patent Document 3 (Japanese Unexamined Patent Publication No. 2009-135140) shown below discloses a semiconductor device including a semiconductor supporting substrate 1, an insulating film having a thickness of not more than 10 nm, and a semiconductor layer 4, in which a first field effect transistor having a first gate electrode 20 and forming a logic circuit is formed in the upper surface of the semiconductor layer 4, and a second field effect transistor having a second gate electrode and forming a memory circuit is formed in the upper surface of the semiconductor layer 4. In the semiconductor supporting substrate 1, at least three or more well regions 6, 6T, 7, and the like of different conductivity types are formed, and the well regions electrically isolate the region of the semiconductor supporting substrate 1 located under the first gate electrode and the region of the semiconductor supporting substrate 1 located under the second gate electrode (see FIG. 5 or the like).
On the other hand, Patent Document 4 (Japanese Unexamined Patent Publication No. 2008-187007) shown below discloses an SRAM cell formed in a SOI substrate. In the SRAM, electrical coupling between the drain region of a driver transistor Q2 and the drain region of a load transistor Q3 and electrical coupling between the drain region of a driver transistor Q5 and the drain region of a load transistor Q6 are respectively achieved by interconnect structures 15 and 16 each formed using a SOI layer 3 under an isolation oxide film 4 serving as a partial trench isolation (see FIG. 5 or the like).